(1) Field of the Invention
The invention relates to a method to testing an integrated circuit device, and, more particularly, to a method of high speed data rate testing using an optimized data strobe for a parallel, multiple circuit, automated test system.
(2) Description of the Prior Art
An important step in the manufacture of integrated circuit devices is testing. Due to the increasing complexity and speed of IC devices, testing presents unique challenges. Typically, IC devices are tested several times in the manufacturing sequence. In particular, individual IC die are tested at the wafer level, prior to sawing and packaging. The packaged parts are then re-tested to insure functionality.
A challenging circuit testing scenario involves very high speed devices. In particular, high data rate devices, such as double data rate (DDR) DRAM devices present a unique challenge for the automated test system. A DDR DRAM is designed to provide data access at a rate of twice the system clock frequency, as will be described below.
Referring now to FIG. 1, an integrated circuit wafer 10 is shown. A plurality of IC circuit die 14 is arrayed across the wafer 10. Two die groups, DIE GROUP A 18 and DIE GROUP B 22, are highlighted. Each die group 18 and 22 comprises an array of four die. A particularly useful concept in the prior art is to test a die group, such as group A or B in the illustration, simultaneously using a multiple die, automatic wafer test system. In this type of system, a die group, typically comprising between about 16 and 32 die, is simultaneously probed. Then the entire die group is simultaneously tested, in parallel, using a common tester program. The data outputs of each die, such as die 1, 2, 3, and 4 in GROUP A, are evaluated independently to determine if each circuit has passed or failed the test. This type of testing scheme is particularly effective on memory devices and represents a significant cost reduction compared to a single die testing system.
Referring now to FIG. 2, an automated test system 25 is shown for testing multiple packaged circuits 26A, 26B, 26C, and 26D. In this case, a group of packaged devices 26A, 26B, 26C, and 26D is tested simultaneously by a multiple circuit, automatic test system 25. This multiple package testing system works the same as the multiple die system of FIG. 1 that is discussed above. Both of these multiple circuit, simultaneous testing systems present unique challenges for tester timing as will be discussed below.
Referring now to FIG. 3, the timing relationships between the test system clock 30, the device under test (DUT) data output lines 34, and the tester data strobe 38 for a double data rate (DDR) DRAM device is shown. The test system clock 30 is generated by the automated test system. In this case, the system clock has a frequency of 250 MHz. The system clock 30 is used to drive the DUT, in this case a DDR DRAM. In response to the test pattern input, the DUT generates an output 34. In this case, the data out signal 34 comprises the data bus lines (D0-Dn) of the DDR DRAM. The DDR DRAM is designed to output data on every half-clock cycle of the system clock such that data out 34 has an effective frequency of 500 MHz or double the system clock rate.
In the illustration, the data out signal 34 is shown as changing states every half-clock cycle. Further, data out 34 takes a finite time to reach final state. The data strobe signal 38 is generated by the tester. The tester uses the data strobe 38 to time the sampling of the data out signal 34. As can be seen from the timing diagram, the timing of the data strobe 38 is critical for accurately acquiring the data output value 34.
Referring now to FIG. 4, a difficulty encountered in multiple circuit testing is illustrated. For example, a multiple circuit test may be performed on the exemplary die groups of FIG. 1 or the package group of FIG. 2. Further, in this example, the DUT devices comprise DDR DRAM devices. Referring again to FIG. 3, the DIE 1 data output 64, DIE 2 data output 68, and DIE 3 data output 72 are shown. The data strobe 60 is also shown. In this case, significant process variation between the plurality of circuits in the circuit group causes significant variation in the timing performance of each circuit. However, a single strobe timing is used for all of the circuit during the simultaneous, parallel test.
As can be seen by the marking points 76, 80, and 84, the data lines 64, 68, and 72, are in different states at the strobe 60 enable. In the prior art, the timing of the data strobe 60 is static. That is, a single strobe timing, with respect to the system clock, is used for every circuit group tested. However, the static strobe timing causes correctly functioning circuit die to fail the test, especially those circuits at the extremes of the processing window. This represents a significant loss of product and profits for the manufacturer.
Several prior art inventions relate to data strobe and to testing. U.S. Pat. No. 6,240,042 to Li describes a method for generating a data strobe signal for a DDR DRAM having improved synchronization. U.S. Pat. No. 4,412,327 to Fox et al discloses a test circuit for testing an IC.